1. Field of the Invention
The present invention relates to a data processing system, and more particularly to a data processing system which can reduce the total time of operation when first and second operands each starting at any desired address of a main memory and having any desired byte length are processed.
2. Description of the Prior Art
In a data processing system, when a variable operand length instruction, such as a decimal operation instruction, is to be processed, it may be processed byte by byte by a one-byte width adder or a plurality of bytes at a time by a four- or eight-byte width adder in order to process at a high speed.
The latter method can process faster that the former method because a plurality of bytes are processed at a time. However, the latter method still has a problem to be resolved in that much time is required to align the operand position. The latter method is more specifically described below. The first operand is shifted to align to a specified byte position. Then, the second operand is shifted to align to the same byte position as the first operand. The first and second operands are then processed. A result of the operation is shifted to align to the first operand position. Thus, three alignments of the operand position, that is, the shift of the first operand, the shift of the second operand and the shift of the operation result are required. As a result, the time required to perform the alignment of the operand position is long relative to the actual operation time and the instruction executive time is not shortened in spite of the provision of the wide width adder.